Field of the Invention and Related Art Statement
The present invention relates to a solid state image sensor comprising a light receiving section including a number of light receiving cells arranged in matrix and a signal readout section for reading an image signal out of the light receiving section, and more particular to a solid state image sensor in which fixed pattern noises can be reduced to a great extent by the simple construction.
In the solid state image sensor, noises are fixedly generated in an image signal regardless of picked-up objects. Such noises are called the fixed noise. As a fixed noise, there are, for example, noises caused by flaw or defect of semiconductor devices constituting light receiving elements, noises caused from lack of uniformity of light receiving cell pattern, switching noise, etc. These noises are generally called "Fixed Pattern Noise" (hereinafter abbreviated as FPN). Such an FPN is caused not only by the defect on the semiconductor devices and the non-uniformity of light receiving cell pattern, but also by a difference in off-set voltage of amplifying elements which are arranged in each light receiving cells, and a difference in gain of each amplifying elements.
FIG. 1 is a block diagram showing a constitution of a conventional solid state image sensor disclosed in Japanese Patent Publication Kokai No. 52-122038, in which said FPN is removed. The solid state image sensor comprises a light receiving section 1 having a plurality of light receiving cells arranged in matrix and a readout section 5 for reading image signals out of each light receiving cells. The readout section 5 comprises a horizontal scanning switch 2, a horizontal scanning shift register 3 for driving the horizontal scanning switch, and a vertical scanning shift register 4. The image signals read out by the readout section 5 are amplified in a pre-amplifier 6, and then are converted to digital image signals by an A/D converter 7. The digital image signal may be stored via a switch SL in a memory 8 which can store the image signals for a period corresponding to one horizontal line scanning period or one field scanning period. After storing the image signals in the memory 8, the switch SL is switched so that output signals from the A/D converter 7 and signals read out of the memory 8 are supplied to an operation circuit 9, and operation (addition, subtraction, multiplication or division) of these signals is done such that the image signals from which FPN is removed can be obtained. Furthermore, the thus obtained digital image signals are converted by a D/A converter 10 into analogue image signals. In this manner, the analogue image signals from which FPN has been removed can be obtained.
In the conventional solid state image sensor mentioned above, it is necessary to arrange the A/D converter 7, memory 8, operation circuit 9 and D/A converter 10 separately from the semiconductor substrate in which the light receiving section 1 and readout section 5 are formed, as a so-called external circuit. Therefore, the known solid state image sensor is liable to be complex in construction and large in size. In the known solid state image sensor, FPN is removed by operating the signals read out of the light receiving section 1 and the signals read out of the memory 8. In general, the memory 8 has only 8 bits per pixel to express 256 tones. Thus, the definition of quantization and the dynamic range are insufficient for removing FPN effectively, and thus the quality of the output image signal is low. In order to remove the FPN sufficiently and obtain a sufficiently wide dynamic range, it is necessary to express a pixel by ten to thirteen bits. Then, the constitution of solid state image sensor will be complex and the cost for manufacturing thereof will be high.